The first part of this talk will focus on cross-layer modeling and design of SOT-MRAM chips based on a comprehensive set of experimentally validated physical models for nanoscale SOT devices and physical design of memory cells, subarrays, peripheral circuits, memory controllers, and the full chip. At the device level, tradeoffs among the write current, error rate, and time will be quantified and will be used to design and optimize memory sub-arrays and to perform DTCO for the entire memory chip based on place and route (PnR). The second part of the talk will present the design and benchmarking of SOT-MRAM content-addressable-memories (CAM) for nearest neighbor search and will show how BEOL compatible Transition Metal Dichalcogenide (TMD) Thin-Film Resistors can be used to significantly improve the resolution of CAMs.