Fuelled by exciting advances in materials and devices, in-memory computing (IMC) architectures represent a promising avenue to transcend the energy-delay bottlenecks of classical Von Neumann systems. While manual designs have demonstrated orders of magnitude improvements in efficiency, the lack of unified software stacks limits their general adoption and design-space exploration. In this talk, we discuss how high-level compiler frameworks can become enablers for top-down design and for the exploration of the vast parameter space of IMC architectures. We report on current efforts to build an integrated compiler framework based on the MLIR infrastructure. By leveraging a multi-level dialect approach, our framework abstracts away individual technology constraints to foster cross-layer re-use. Concretely, we present optimizing flows tailored for diverse IMC primitives—including cross-bars, content-addressable memories (CAMs), and bulk-wise logic operations. We argue that such integrated automation is key to navigating the increasingly heterogeneous landscape of emerging accelerators and bringing their benefits to a broader range of applications.