Integrating Optical Probing Security Evaluation Framework Into ASIC Design Flow
Sajjad Parvin (U Bremen), Frank Sill Torres (DLR), Rolf Drechsler (U Bremen an DFKI)

Limitations of Architectural Simulation for Security: Why Transient-Execution Countermeasures Must Be Designed and Evaluated on the RTL
Tobias Jauch, Philipp Schmitz, Alex Wezel, Simón Blanko Ortiz, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz (RPTU Kaiserslautern-Landau)

Modeling of Tamper Resistance to Correlative Electromagnetic Analysis for Voltage-scaled Circuits
Yusuke Matsubayashi, Kazuki Minamiguchi, Hiroki Nishikawa, Yoshihiro Midoh, Noriyuki Miura and Jun Shiomi (U Osaka)