This talk presents an ongoing evaluation of a Very-Wide-Register Coarse-Grained Reconfigurable Arrays (CGRAs) and a RISC-V GPU for edge computing nodes within the ESL EPFL. We are currently performing an analysis of these architectures in TSMC 16nm technology, aiming to identify optimal solutions for diverse computational workloads. This work is still in progress, but we will discuss preliminary findings, and insights, including HW and SW extensions for the open-source Vortex GPGPU. Furthermore, we will present three more CGRA designs, two of which have also been fabricated in TSMC 65nm LP. We will present initial results, highlighting their performance characteristics and potential applications. All of these accelerators are being integrated within the X-HEEP platform, a versatile RISC-V microcontroller system. X-HEEP leverages a rich ecosystem of open-source IPs, including CPUs from the OpenHW Group, uncore IPs from the PULP platform and OpenTitan project, and custom IPs. X-HEEP enables seamless integration and rapid prototyping. We will discuss the integration process and demonstrate how X-HEEP facilitates the evaluation and deployment of custom accelerators.