In this talk, we will first describe a novel hardware architecture that merges in-memory computing with a RISC-V core to significantly reduce energy consumption and latency for TinyML tasks. Then, we detail MATCH, a flexible compiler, built on the TVM framework, designed to optimize AI workloads across heterogeneous edge systems prioritizing efficiency. Finally, we will demonstrate the full pipeline by deploying a deep neural network onto the presented hardware using MATCH, showcasing the flexibility of the compilation tool and the efficiency of the in-memory accelerator.