Multiple research vectors represent possible paths to improved energy and performance metrics at the application-level. There are active efforts with respect to emerging logic devices, new memory technologies, novel interconnects, and heterogeneous integration architectures. Of great interest is quantifying the potential impact of a given solution to prioritize research vectors accordingly.  Ideally, any such comparisons should be made to state-of-the-art/scaled CMOS solutions in an application-level context.  In this presentation, students from SUPREME PI Michael Niemier’s group consider how ferroelectric-based associative memories may be employed for different workloads, and present layout-based analysis to show how said solutions may ultimately compare to highly scaled CMOS solutions across different figures of merit.  Directions and suggestions for future efforts at the algorithmic, layout/chip-design, and materials science-levels – to derive maximum benefits from technology – will also be briefly discussed.